IBM Research Alliance Builds New 5nm Transistor

8 June, 2017

IBM, GLOBALFOUNDRIES and Samsung have developed a new process to build smaller and better transistors than the current FinFET, which is the blueprint for the semiconductor industry up through 7nm

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IBM Research Alliance (IBM, GLOBALFOUNDRIES, Samsung, and equipment suppliers) have developed an industry process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips. The details of the process will be presented at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. This new technology paves the way for 30 billion switches on a single silicon die.

Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor. IBM Research has explored nanosheet semiconductor technology for more than 10 years. It believes that the electrical properties of its new nanosheet devices are superior to FinFET architecture which is the blueprint for the semiconductor industry up through 7nm node technology.

Better than FinFET

Compared to the leading edge 10nm technology available in the market, a nanosheet-based 5nm technology can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance. Gary Patton, CTO and Head of Worldwide R&D at GLOBALFOUNDRIES said: “As we make progress toward commercializing 7nm in 2018 at our Fab 8 manufacturing facility, we are actively pursuing next-generation technologies at 5nm and beyond to maintain technology leadership and enable our customers to produce a smaller, faster, and more cost efficient generation of semiconductors.”

IBM Researcher with Silicon Wafer
IBM Research scientist Nicolas Loubet holds a wafer of chips with 5nm silicon nanosheet transistors

The same Extreme Ultraviolet (EUV) lithography approach used to produce the 7nm test node was applied to the nanosheet transistor architecture. Using EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing process.

This adjustability permits the fine-tuning of performance and power for specific circuits – something not possible with today’s FinFET transistor architecture production, which is limited by its current-carrying fin height. Therefore, while FinFET chips can scale to 5nm, simply reducing the amount of space between fins does not provide increased current flow for additional performance.

The silicon nanosheet transistor demonstration was detailed in the paper Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET, published by VLSI. IBM says it proves that 5nm chips are possible, more powerful, and not too far off in the future.

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