Orbotech PVD Solution Selected for imec 3D System Integration Program

23 July, 2017

3D System Integration Program is aimed to reduce the cost per function of semiconductors by moving to a 3-Dimensional stacking of ICs (3D-IC)

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Orbotech’s SPTS Technologies, has been named by imec as a new supplier for its 3D System Integration Program. SPTS will supply physical vapor deposition (PVD) solutions for under bump metallization (UBM) and redistribution layer (RDL) processes for next generation fan-out packaging technologies. Imec has selected SPTS’s Sigma fxP PVD solution as the new process tool of record (PTOR) for low temperature PVD for development of novel fan-out technologies such as flexible micro-bumps for chip scale packaging.

“Novel 3D integrated circuit (IC) architectures need to be developed to meet scaling challenges without compromising cost, performance, and power budgets,” said Kevin Crofton, President of SPTS Technologies and Corporate Vice President at Orbotech. ”Imec works closely with leading semiconductor companies to develop innovative wafer-level packaging architectures that will meet the performance requirements of next generation devices. We are proud that imec selected SPTS for its 3D System Integration Program, and we look forward to working with imec and its partners in developing innovative interconnect and fan-out technologies.”

The 3D System Integration Program is aimed to reduce the cost per function of semiconductors by moving to a 3-Dimensional stacking of ICs (3D-IC). Using 3D chip stacking, it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling. imec’s R&D on 3D-IC technology explores cost-effective 3D interconnect technology with through-silicon-via (TSV), 3D design to propose methodologies for critical design issues.

It also explores Electrical, thermal and thermo-mechanical characterization and optimization, Chip-package interactionand Cost modeling. The Sigma fxP is a cluster PVD system used by device manufacturers in various end markets including power management, MEMS and RF devices.  In semiconductor packaging, the Sigma fxP deposits RDL and under bump metals (UBM) for Cu micropillar and TSV’s, plus TSV liner/barrier for 3DWLP.

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